Sigma-delta digital-to-analog converters (SD DACs) are often used in mixed signal integrated circuits (ICs) that combine digital and analog circuits on the same substrate. Generally, SD DACs consist of a two-state voltage translator followed by a low-pass filter (LPF). The voltage accuracy of the overall SD DAC is generally determined by the input voltage translator.
FIG. 1 is a circuit diagram of an example of a typical SD DAC 100. SD DAC 100 includes a voltage translator stage 102 coupled with a low pass filter 104. The voltage translator stage 102 provides a replica of an input digital signal (DIN) 106 that switches between two relatively stable and accurate voltage references, VP and VN. It is possible to use a simple 1-to-1 translator in which the VP voltage is the same as the logic high voltage (or supply voltage) of the DIN signal and the VN voltage is the logic low voltage of the DIN signal (or ground). However, this approach is avoided in high precision systems due to various artifacts. These artifacts include, but are not limited to, supply voltage temperature effects, supply voltage loading effects, and various uncontrolled IR drops (i.e., noise) in the both the ground and supply loops.
The steady state output voltage of an SD DAC is proportional to the density-of-ones, or equivalent duty cycle, d, of the input data stream. For SD DAC 100, the steady state output voltage may be expressed as follows.VOUT=d(DIN)(VP+VN)−VN For d(DIN)=0, VOUT=−VN. For d(DIN)=1, VOUT=VP. For d(DIN)=0.5, VOUT=0.5(VP−VN). If VP=VN, then for d(DIN)=0.5, VOUT=0. As is known in the art, VOUT=0 is an important condition for proper performance of an SD DAC. For example, VOUT=0 is an important condition for rebalancing accelerometers such as MEMS based accelerometers. Therefore, what happens if VP is not equal to VN is of great concern.
Generally, there are two classes of errors that can be labeled as offset errors and gain errors. These errors may affect the performance of an SD DAC. Both offset errors and gain errors may be defined in terms of an external reference voltage, VR.
Offset errors occur when VP≠VN. Gain errors occur when the average magnitude of VP and VN differs from VR. That is, gain errors occur when (VP+VN)≠2VR. It is possible to have gain errors without offset errors if VP=VN. Likewise, it is possible to have offset errors without gain errors if (VP+VN)=2VR. However, both types of errors generally will occur together in most systems.
The offset voltage component, VOF, may be computed as follows.VOF=(VP−VN)/2Generally, however, it is more useful to know how VOF compares to VR than to have the absolute voltage value of VOF. Therefore, it is useful to define a relative offset error in terms of a dimensionless quantity, EOF. By definition,EOF=VOF/VR=(VP−VN)/2VR.
Gain error, EG, may be calculated from the gain of the SD DAC. The gain of an SD translator, G, may be defined as follows.G=(VP+VN)/2VR Nominally, G is unity for VP=VN=VR. Gain error, EG, is also a dimensionless quantity and may be defined asEG=G−1=(VP+VN−2VR)/2VR.
Rather than expressing EOF and EG as above, it is often useful and more convenient to express EOF and EG differently. For instance, let EP=(VP−VR)/VR represent the relative error of the positive reference voltage and EN=(VN−VR)/VR represent the relative error of the negative reference voltage. EOF and EG may be expressed in terms of these error components.EOF=(EP−EN)/2EG=(EP+EN)/2
The offset and gain errors affect the output voltage of an SD DAC. Therefore, when offset error and gain error effects are included, the output voltage of an SD DAC is modified as shown in the equations below.VOUT=Gd(DIN)(VP+VN)−VN+VOF VOUT=(1+EG)d(DIN)(VP+VN)−VN+(EOFVR)
Current SD DAC designs have gain and offset errors that require correction in order to operate at a high precision. It may be possible to overcome these errors in an SD DAC in the digital domain by slight modifications applied to the density-of-ones pattern of the input data stream. However, making such modifications requires additional digital hardware, firmware, and/or software. An SD DAC with reduced offset and gain errors would require less hardware, firmware, and/or software to compensate for offset and gain errors than would an SD DAC with higher errors. Additionally, in some systems, an SD DAC with reduced offset and gain errors may eliminate the need for any means of correction. Therefore, it is highly desirable to reduce these error terms as much as possible at the translator stage in SD DACs. Thus, it would be beneficial to have an SD DAC where these offset and gain errors are reduced.